1. Field of the Invention
The present invention relates to a solid-state imaging device.
2. Description of the Related Art
In general, solid-state imaging devices used for digital cameras or digital video include an AD converter to convert an image signal of analog values to digital values. Various types of AD converters are known, and one type of them is a ramp-type AD converter. In a ramp-type AD converter, relative magnitudes of an input analog signal and a ramp signal are compared using a comparator, and a period from the time when the ramp signal starts to change until the time when the output of the comparator inverts is measured to determine the digital value. Although ramp-type AD converters can be configured with a small scale circuit, this is not suitable for a high speed operation because 2(n−1) clock cycles are required to perform the AD conversion with n-bit resolution. Another AD converter type is referred to as a successive-approximation AD converter. Successive-approximation AD converters, which include a plurality of capacitors having binary weighted capacitance values, change a comparison signal using the capacitors, and continue to halve the range where the analog value is included. Although successive-approximation AD converters are suitable for high speed operation because n-bit resolution is realized in n clock cycles, their circuit scale becomes large because the capacitance ratio of the capacitors (i.e. area ratio) becomes 1:2(n−1) at a maximum.
Considering the current situation, Japanese Patent Laid-Open No. 2012-54913 proposes a hybrid type AD converter. In the AD converter, a sub-range including the digital value is determined using a plurality of capacitors, and the digital value is determined from the sub-range by using a ramp signal.